1. Field of the Disclosure
The disclosure relates generally to integrated circuit design and, more particularly, to techniques for detecting and correcting errors in integrated circuit design.
2. Brief Description of Related Technology
The dramatic increase in design complexity of modern electronics challenges the ability of developers to ensure their functional correctness. While improvements in verification allow engineers to find a larger fraction of design errors more efficiently, little effort has been devoted to fixing such errors. As a result, debugging remains an expensive and challenging task.
To address this problem, researchers have recently started to propose techniques that automate the debugging process, by locating the error source within a design and/or by suggesting possible corrections. The root causes of functional errors can be several, ranging from poor specifications, miscommunication among designers, or conceptual or typing mistakes by a designer. Often these errors occur in the Register-Transfer Level (RTL) description of a design because most design activities are carried out at this level. RTL abstraction is used in hardware description languages (HDLs) to create high-level representations of a circuit, from which lower-level representations and wiring actualization can be derived. Although in theory errors can be corrected either at the RTL or the gate level, most solutions proposed in the literature use a gate-level description (netlist) as the underlying model. On one hand, this model presents some valuable advantages. For instance, RTL modifications at late design stages are undesirable because they may invalidate previous optimizations and hamper design closure; errors due to flawed synthesis tools are also only visible at the gate level. Finally, hard-IP blocks usually do not have an associated RTL description.
On the other hand, fixing errors at the RTL could offer several important advantages not available at the gate level. First, error diagnoses are generally most readily understood at the RTL. Second, in an RTL block the change propagates to all netlists synthesized from that code, while a correction at the gate level is only effective for one netlist. Third, corrections at the RTL require fewer changes, which are more effective, since in general a single erroneous RTL statement may affect a large portion of the corresponding netlist. In addition, the complexity of locating the source of bugs at the gate level grows considerably for compound errors (that is, when several error sources are present in the same design). Finally, since mapping the results of gate-level diagnosis back to the RTL is a difficult task, most often RTL errors can only be located through an RTL-based analysis.
To support this effort, tools such as waveform viewers and simulation assertions are often used at the forefront of debugging activities in industry. However, even with these tools, diagnosing the root cause of an error and fixing it still requires engineers' expertise, time, and effort. Existing techniques that address these problems range in their scope. For instance, the algorithms developed by Shi et al. “An Efficient Approach for Error Diagnosis in HDL Design”, in Proc ISCAS, 2003, pp. 732-735, Jiang et al., “Estimating Likelihood of Correctness for Error Candidates to Assist Debugging Faulty HDL Designs,” ISCAS, 2005, pp. 5682-5685 and Rau et al., “An Efficient Mechanism for Debugging RTL Description”, IWSOC, 2003, pp. 370-373 generate lists of potentially error locations. Bloem and Wotawa, “Verification and Fault Localization for VHDL Programs”, Journal of the Telematics Engineering Society (TIV), pp. 30-33, Vol. 2, 2002 take a different approach by formally analyzing an HDL description and its failed properties. Because of this their technique can only be deployed in a formal verification framework and cannot be applied in a simulation-based verification flow common in the industry today.
The work by Staber et al., “Finding and Fixing Faults”, in CHARME, Springer-Verlag LNCS 3725, 2005, pp. 35-49 can diagnose and correct RTL design errors automatically, but it relies on state-transition analysis and hence, it does not scale beyond tens of state bits. In addition, this algorithm requires a correct formal specification of the design, which is rarely available in today's design environments, because its development is often as challenging as the design process itself. In contrast, the most common type of specification available is a high-level model, often written in a high-level language, which produces the correct I/O behavior of the system.
To develop a scalable and powerful RTL error diagnosis and correction system, a set of fundamentally new constructs and algorithms are desired.